vllm.models.kimi_k3.amd.specialized_decode.mono.common.ops
¶
Device-side primitives of the mono kernels: wave reductions and shuffles, the approximate hardware math, bf16 / fp8 packing, buffer resources, the execution-model constants and the kernel symbol naming.
Ported from the FlyDSL GLM-5 layer kernel (ROCm/FlyDSL branch
glm5-mla-moe-layer-monokernel @ 1e28fd8a,
kernels/mla_moe_layer/shared_reuse_moe_kernel.py). Only published flydsl APIs
and aiter's vendored buffer_ops / dpp_utils are used.
Every function but kernel_symbol is traced inside a @flyc.kernel body.
Raw boundaries kept, for want of an equivalent on the pinned FlyDSL:
buffer_ops loads / stores (the kernels take raw Int64 addresses, no tensors
for make_buffer_tensor); raw MFMA intrinsics (hand-laid operands: permlane
transposes, fp8 packing, MXFP4 scales); the LLVM intrinsics here (expect,
s_memrealtime, the approximate rsq / rcp / exp2) and the struct unpacking of
permlane*_swap.
Functions:
-
ballot–The wave's lanes where
predholds, a bit a lane. -
batched_rounds–A CTA's strided loop over elements v = tid + THREADS i < n (n a Python
-
bf16_pair–Two f32 -> one f32-typed word holding (bf16(a), bf16(b)).
-
bf2_f32–Packed bf16 pair word -> (f32 low, f32 high).
-
bf_hi–The f32 of a packed bf16 pair word's high half.
-
bf_lo–The f32 of a packed bf16 pair word's low half.
-
block_excl_scan–(exclusive prefix of v over the CTA in thread order, CTA total);
buf -
block_max–Max of v over the CTA's WAVES waves;
redneeds WAVES words. -
butterfly–Butterfly reduction over the given xor offsets, in the given order.
-
div_rn–x / drounded to nearest, bit-identical to the IEEE division, given -
fp8_pack4–Four f32 (already in range) -> one dword of four E4M3 bytes, RNE.
-
fp8x8_bf16_pk–Eight fp8 of two dwords -> bf16 MFMA operand (exact) by
-
fresh–v(a per-lane Int32) through an opaque move, here: the lane math built -
global_load–wordsi32 (1, 2 or 4) at the 64-bit global addressaddr. A pool -
hw_rsq–v_rsq_f32 (~1 ulp, no libm range fixups).
-
kernel_symbol–Kernel symbol that profilers demangle to
atom::<stem>_<params>. The -
lane_gather–Lane
src_lane's value of v, a source lane a lane (ds_bpermute). -
lanes_below–How many of the lanes in ballot
balare belowlane. -
ld_dev–wordsi32 (1, 2 or 4) of a buffer from wordi, at device scope -
ld_i32–Word
iof a buffer, a plain Int32 load. -
lds_bytes–The LDS an
fx.structclass takes, alignment included. -
load_ptr64–Entry
iof an i64 table in memory, wave-uniform (each half through -
memrealtime–s_memrealtime: the 100 MHz device clock (no FlyDSL wrapper).
-
mfma_fp8–16x16x32 fp8 x fp8 MFMA, unscaled:
a/ban i64 of 8 E4M3 each. -
permlane_swap–v_permlane{32,16}_swap on registers (x, y): off 32 trades x's upper-half
-
readlane–Lane
src_lane's value of v (wave-uniform). -
row_live–Whether row k of the step is a request's: its
batch_id_per_q_token -
row_shr–DPP row_shr:k of an f32: lane - k of the same 16-lane row, else 0.
-
row_sum–Row r, token t of the waves' 16x16 MFMA accumulators (wave w's at
red -
rows_to_lds–rowsrows ofrow_wordswords (a multiple of 4) read at device scope -
traced–Apply flydsl's AST rewriting to a helper, so its
while/ifover -
unlikely–condmarked cold (llvm.expect): LLVM lays the branch out of the hot -
wave_incl_scan–Inclusive prefix sum of an Int32 over the wave, in lane order.
-
xred–op(v, lane ^ off) for a symmetric op; 32 / 16 take both halves of one swap.
-
xshfl–Value of lane
lane ^ off: offsets 32 / 16 via v_permlane*_swap, in-row
_xpartner(v, off, lane)
¶
Lane lane ^ off's v: DPP within a row, v_permlane*_swap across rows
(xshfl takes shuffle_xor there).
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
ballot(pred)
¶
batched_rounds(tid, n, load, use, batch=LOAD_BATCH)
¶
A CTA's strided loop over elements v = tid + THREADS i < n (n a Python
int): load(v) of batch rounds issued before any use(v, loaded).
A round whose use stores to global memory keeps the next round's loads
behind it (they may alias), so the rounds' loads would go out in series. A
round past n loads element n - 1 (in range) and uses nothing.
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
bf16_pair(a, b)
¶
Two f32 -> one f32-typed word holding (bf16(a), bf16(b)).
bf2_f32(w)
¶
bf_hi(w)
¶
bf_lo(w)
¶
block_excl_scan(v, lane, wave, buf)
¶
(exclusive prefix of v over the CTA in thread order, CTA total); buf
needs WAVES words.
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
block_max(v, lane, wave, red)
¶
Max of v over the CTA's WAVES waves; red needs WAVES words.
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
butterfly(v, offsets, op=_add)
¶
Butterfly reduction over the given xor offsets, in the given order.
The order is the numerical contract: the aiter per-head norm reduces 32 lanes with offsets 16, 8, 4, 2, 1, and matching it keeps rstd bit-exact.
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
div_rn(x, d, r)
¶
x / d rounded to nearest, bit-identical to the IEEE division, given
r = 1.0 / d from one true division per divisor (Markstein: a quotient
within 1 ulp plus its exact fma residual times RN(1/d) rounds correctly).
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
fp8_pack4(a, b, c, d)
¶
Four f32 (already in range) -> one dword of four E4M3 bytes, RNE.
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
fp8x8_bf16_pk(words)
¶
Eight fp8 of two dwords -> bf16 MFMA operand (exact) by v_cvt_scalef32_pk_bf16_fp8 (scale 1), two values an instruction.
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
fresh(v)
¶
v (a per-lane Int32) through an opaque move, here: the lane math built
on it is computed at its use, where LLVM would otherwise hoist it out of a task
loop or CSE it across stages into registers held for the whole kernel (spills,
and a kernel with scratch is refused: runtime.widths).
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
global_load(addr, words=1, nt=False)
¶
words i32 (1, 2 or 4) at the 64-bit global address addr. A pool
past 4 GiB is reached only this way: a buffer load's offset (index x stride
included) is 32 bits. nt: nontemporal.
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
hw_rsq(x)
¶
kernel_symbol(stem, **params)
¶
Kernel symbol that profilers demangle to atom::<stem>_<params>. The
amdhsa assembler rejects :: in a symbol, so it is Itanium-mangled, as
aiter's _ZN5aiter...E kernels are.
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
lane_gather(v, src_lane)
¶
Lane src_lane's value of v, a source lane a lane (ds_bpermute).
lanes_below(bal, lane)
¶
ld_dev(ptr, i, words=1)
¶
words i32 (1, 2 or 4) of a buffer from word i, at device scope
(past the per-XCD L2).
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
ld_i32(ptr, i)
¶
lds_bytes(struct)
¶
load_ptr64(table, i)
¶
Entry i of an i64 table in memory, wave-uniform (each half through
uniform): a peer's buffer base, a kernel argument block's pointer.
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
memrealtime()
¶
s_memrealtime: the 100 MHz device clock (no FlyDSL wrapper).
mfma_fp8(a, b, c)
¶
16x16x32 fp8 x fp8 MFMA, unscaled: a / b an i64 of 8 E4M3 each.
permlane_swap(off, x, y)
¶
v_permlane{32,16}_swap on registers (x, y): off 32 trades x's upper-half lanes with y's lower-half lanes; off 16 trades x's odd 16-lane rows with y's even rows (each within its half). -> (x', y').
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
readlane(v, src_lane)
¶
Lane src_lane's value of v (wave-uniform).
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
row_live(batch_ids, k)
¶
Whether row k of the step is a request's: its batch_id_per_q_token
entry, -1 on a CUDA-graph pad row (wave-uniform for a uniform k). A pad row
runs like any other but joins no decision another row's work depends on.
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
row_shr(v, lane, k)
¶
DPP row_shr:k of an f32: lane - k of the same 16-lane row, else 0.
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
row_sum(red, r, t, waves=None)
¶
Row r, token t of the waves' 16x16 MFMA accumulators (wave w's at red
+ (w * 64 + lane) * 4), summed in wave order from 0 (waves: which, in
order; all of them by default).
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
rows_to_lds(tid, src, rows, row_words, dst, dst_row)
¶
rows rows of row_words words (a multiple of 4) read at device scope
from address src -> LDS dst, a row every dst_row words: 16 B a
lane, the loads batched (batched_rounds).
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
traced(fn)
¶
Apply flydsl's AST rewriting to a helper, so its while / if over
traced values lower to scf ops. Kernels rewrite only their own body.
unlikely(cond)
¶
cond marked cold (llvm.expect): LLVM lays the branch out of the hot
path. A rare path's code inline among the hot stages costs them even when it
never runs (the long-context selection: S = 16, 3k context +1.4 us).
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
wave_incl_scan(v, lane)
¶
Inclusive prefix sum of an Int32 over the wave, in lane order.
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
xred(v, off, op)
¶
op(v, lane ^ off) for a symmetric op; 32 / 16 take both halves of one swap.
Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
xshfl(v, off)
¶
Value of lane lane ^ off: offsets 32 / 16 via v_permlane*_swap, in-row
offsets via DPP (VALU latency, not LDS). Powers of two only: any other
offset would take the lane ^ 1 path.