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vllm.models.kimi_k3.amd.specialized_decode.mono.common.ops

Device-side primitives of the mono kernels: wave reductions and shuffles, the approximate hardware math, bf16 / fp8 packing, buffer resources, the execution-model constants and the kernel symbol naming.

Ported from the FlyDSL GLM-5 layer kernel (ROCm/FlyDSL branch glm5-mla-moe-layer-monokernel @ 1e28fd8a, kernels/mla_moe_layer/shared_reuse_moe_kernel.py). Only published flydsl APIs and aiter's vendored buffer_ops / dpp_utils are used.

Every function but kernel_symbol is traced inside a @flyc.kernel body.

Raw boundaries kept, for want of an equivalent on the pinned FlyDSL: buffer_ops loads / stores (the kernels take raw Int64 addresses, no tensors for make_buffer_tensor); raw MFMA intrinsics (hand-laid operands: permlane transposes, fp8 packing, MXFP4 scales); the LLVM intrinsics here (expect, s_memrealtime, the approximate rsq / rcp / exp2) and the struct unpacking of permlane*_swap.

Functions:

  • ballot –

    The wave's lanes where pred holds, a bit a lane.

  • batched_rounds –

    A CTA's strided loop over elements v = tid + THREADS i < n (n a Python

  • bf16_pair –

    Two f32 -> one f32-typed word holding (bf16(a), bf16(b)).

  • bf2_f32 –

    Packed bf16 pair word -> (f32 low, f32 high).

  • bf_hi –

    The f32 of a packed bf16 pair word's high half.

  • bf_lo –

    The f32 of a packed bf16 pair word's low half.

  • block_excl_scan –

    (exclusive prefix of v over the CTA in thread order, CTA total); buf

  • block_max –

    Max of v over the CTA's WAVES waves; red needs WAVES words.

  • butterfly –

    Butterfly reduction over the given xor offsets, in the given order.

  • div_rn –

    x / d rounded to nearest, bit-identical to the IEEE division, given

  • fp8_pack4 –

    Four f32 (already in range) -> one dword of four E4M3 bytes, RNE.

  • fp8x8_bf16_pk –

    Eight fp8 of two dwords -> bf16 MFMA operand (exact) by

  • fresh –

    v (a per-lane Int32) through an opaque move, here: the lane math built

  • global_load –

    words i32 (1, 2 or 4) at the 64-bit global address addr. A pool

  • hw_rsq –

    v_rsq_f32 (~1 ulp, no libm range fixups).

  • kernel_symbol –

    Kernel symbol that profilers demangle to atom::<stem>_<params>. The

  • lane_gather –

    Lane src_lane's value of v, a source lane a lane (ds_bpermute).

  • lanes_below –

    How many of the lanes in ballot bal are below lane.

  • ld_dev –

    words i32 (1, 2 or 4) of a buffer from word i, at device scope

  • ld_i32 –

    Word i of a buffer, a plain Int32 load.

  • lds_bytes –

    The LDS an fx.struct class takes, alignment included.

  • load_ptr64 –

    Entry i of an i64 table in memory, wave-uniform (each half through

  • memrealtime –

    s_memrealtime: the 100 MHz device clock (no FlyDSL wrapper).

  • mfma_fp8 –

    16x16x32 fp8 x fp8 MFMA, unscaled: a / b an i64 of 8 E4M3 each.

  • permlane_swap –

    v_permlane{32,16}_swap on registers (x, y): off 32 trades x's upper-half

  • readlane –

    Lane src_lane's value of v (wave-uniform).

  • row_live –

    Whether row k of the step is a request's: its batch_id_per_q_token

  • row_shr –

    DPP row_shr:k of an f32: lane - k of the same 16-lane row, else 0.

  • row_sum –

    Row r, token t of the waves' 16x16 MFMA accumulators (wave w's at red

  • rows_to_lds –

    rows rows of row_words words (a multiple of 4) read at device scope

  • traced –

    Apply flydsl's AST rewriting to a helper, so its while / if over

  • unlikely –

    cond marked cold (llvm.expect): LLVM lays the branch out of the hot

  • wave_incl_scan –

    Inclusive prefix sum of an Int32 over the wave, in lane order.

  • xred –

    op(v, lane ^ off) for a symmetric op; 32 / 16 take both halves of one swap.

  • xshfl –

    Value of lane lane ^ off: offsets 32 / 16 via v_permlane*_swap, in-row

_xpartner(v, off, lane)

Lane lane ^ off's v: DPP within a row, v_permlane*_swap across rows (xshfl takes shuffle_xor there).

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def _xpartner(v, off, lane):
    """Lane ``lane ^ off``'s v: DPP within a row, v_permlane*_swap across rows
    (``xshfl`` takes ``shuffle_xor`` there)."""
    if off < 16:
        return xshfl(v, off)
    a, b = permlane_swap(off, v, v)
    return ((lane & off) != 0).select(a, b)

ballot(pred)

The wave's lanes where pred holds, a bit a lane.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def ballot(pred):
    """The wave's lanes where ``pred`` holds, a bit a lane."""
    return fx.Int64(rocdl.ballot(T.i64, as_ir_value(pred)))

batched_rounds(tid, n, load, use, batch=LOAD_BATCH)

A CTA's strided loop over elements v = tid + THREADS i < n (n a Python int): load(v) of batch rounds issued before any use(v, loaded). A round whose use stores to global memory keeps the next round's loads behind it (they may alias), so the rounds' loads would go out in series. A round past n loads element n - 1 (in range) and uses nothing.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
@traced
def batched_rounds(tid, n, load, use, batch=LOAD_BATCH):
    """A CTA's strided loop over elements v = tid + THREADS i < n (n a Python
    int): ``load(v)`` of ``batch`` rounds issued before any ``use(v, loaded)``.
    A round whose ``use`` stores to global memory keeps the next round's loads
    behind it (they may alias), so the rounds' loads would go out in series. A
    round past n loads element n - 1 (in range) and uses nothing."""
    rounds = -(-n // THREADS)
    for b0 in range_constexpr(0, rounds, batch):
        idx = range(b0, min(b0 + batch, rounds))
        got = [load(fx.min(tid + THREADS * i, n - 1)) for i in idx]
        for i, g in zip(idx, got):
            v = tid + THREADS * i
            if v < n:
                use(v, g)

bf16_pair(a, b)

Two f32 -> one f32-typed word holding (bf16(a), bf16(b)).

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def bf16_pair(a, b):
    """Two f32 -> one f32-typed word holding (bf16(a), bf16(b))."""
    return (
        fx.Vector.from_elements([a, b], fx.Float32)
        .to(fx.BFloat16)
        .bitcast(fx.Float32)[0]
    )

bf2_f32(w)

Packed bf16 pair word -> (f32 low, f32 high).

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def bf2_f32(w):
    """Packed bf16 pair word -> (f32 low, f32 high)."""
    return bf_lo(w), bf_hi(w)

bf_hi(w)

The f32 of a packed bf16 pair word's high half.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def bf_hi(w):
    """The f32 of a packed bf16 pair word's high half."""
    return (w & fx.Int32(-65536)).bitcast(fx.Float32)

bf_lo(w)

The f32 of a packed bf16 pair word's low half.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def bf_lo(w):
    """The f32 of a packed bf16 pair word's low half."""
    return (w << 16).bitcast(fx.Float32)

block_excl_scan(v, lane, wave, buf)

(exclusive prefix of v over the CTA in thread order, CTA total); buf needs WAVES words.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
@traced
def block_excl_scan(v, lane, wave, buf):
    """(exclusive prefix of v over the CTA in thread order, CTA total); ``buf``
    needs WAVES words."""
    incl = wave_incl_scan(v, lane)
    gpu.barrier()
    if lane == 63:
        fx.ptr_store(incl, buf + wave)
    gpu.barrier()
    off = fx.Int32(0)
    tot = fx.Int32(0)
    for w in range_constexpr(WAVES):
        cnt = fx.ptr_load(buf + w)
        off = off + (w < wave).select(cnt, 0)
        tot = tot + cnt
    return incl - v + off, tot

block_max(v, lane, wave, red)

Max of v over the CTA's WAVES waves; red needs WAVES words.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
@traced
def block_max(v, lane, wave, red):
    """Max of v over the CTA's WAVES waves; ``red`` needs WAVES words."""
    wv = wave_max(v)
    gpu.barrier()
    if lane == 0:
        fx.ptr_store(wv, red + wave)
    gpu.barrier()
    t = fx.ptr_load(red + 0)
    for w in range_constexpr(1, WAVES):
        t = fx.max(t, fx.ptr_load(red + w))
    gpu.barrier()
    return t

butterfly(v, offsets, op=_add)

Butterfly reduction over the given xor offsets, in the given order.

The order is the numerical contract: the aiter per-head norm reduces 32 lanes with offsets 16, 8, 4, 2, 1, and matching it keeps rstd bit-exact.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def butterfly(v, offsets, op=_add):
    """Butterfly reduction over the given xor offsets, in the given order.

    The order is the numerical contract: the aiter per-head norm reduces 32
    lanes with offsets 16, 8, 4, 2, 1, and matching it keeps rstd bit-exact."""
    for off in offsets:
        v = xred(v, off, op)
    return v

div_rn(x, d, r)

x / d rounded to nearest, bit-identical to the IEEE division, given r = 1.0 / d from one true division per divisor (Markstein: a quotient within 1 ulp plus its exact fma residual times RN(1/d) rounds correctly).

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def div_rn(x, d, r):
    """``x / d`` rounded to nearest, bit-identical to the IEEE division, given
    ``r = 1.0 / d`` from one true division per divisor (Markstein: a quotient
    within 1 ulp plus its exact fma residual times RN(1/d) rounds correctly)."""
    q = x * r
    return fx.Float32(fmath.fma(fx.Float32(fmath.fma(-q, d, x)), r, q))

fp8_pack4(a, b, c, d)

Four f32 (already in range) -> one dword of four E4M3 bytes, RNE.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def fp8_pack4(a, b, c, d):
    """Four f32 (already in range) -> one dword of four E4M3 bytes, RNE."""
    lo = fx.Int32(rocdl.cvt_pk_fp8_f32(T.i32, a, b, fx.Int32(0), False))
    return fx.Int32(rocdl.cvt_pk_fp8_f32(T.i32, c, d, lo, True))

fp8x8_bf16_pk(words)

Eight fp8 of two dwords -> bf16 MFMA operand (exact) by v_cvt_scalef32_pk_bf16_fp8 (scale 1), two values an instruction.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def fp8x8_bf16_pk(words):
    """Eight fp8 of two dwords -> bf16 MFMA operand (exact) by
    v_cvt_scalef32_pk_bf16_fp8 (scale 1), two values an instruction."""
    out = []
    for w in words:
        for hi in (False, True):
            p = rocdl.cvt_scalef32_pk_bf16_fp8(
                T.bf16x2, as_ir_value(fx.Int32(w)), as_ir_value(fx.Float32(1.0)), hi
            )
            out.append(fx.Vector(p).bitcast(fx.Int32)[0])
    return fx.Vector.from_elements(out, fx.Int32).bitcast(fx.BFloat16)

fresh(v)

v (a per-lane Int32) through an opaque move, here: the lane math built on it is computed at its use, where LLVM would otherwise hoist it out of a task loop or CSE it across stages into registers held for the whole kernel (spills, and a kernel with scratch is refused: runtime.widths).

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def fresh(v):
    """``v`` (a per-lane Int32) through an opaque move, here: the lane math built
    on it is computed at its use, where LLVM would otherwise hoist it out of a task
    loop or CSE it across stages into registers held for the whole kernel (spills,
    and a kernel with scratch is refused: ``runtime.widths``)."""
    return fx.Int32(
        llvm.inline_asm(
            T.i32, [fx.Int32(v).ir_value()], "v_mov_b32 $0, $1", "=v,v",
            has_side_effects=True,
        )
    )  # fmt: skip

global_load(addr, words=1, nt=False)

words i32 (1, 2 or 4) at the 64-bit global address addr. A pool past 4 GiB is reached only this way: a buffer load's offset (index x stride included) is 32 bits. nt: nontemporal.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def global_load(addr, words=1, nt=False):
    """``words`` i32 (1, 2 or 4) at the 64-bit global address ``addr``. A pool
    past 4 GiB is reached only this way: a buffer load's offset (index x stride
    included) is 32 bits. ``nt``: nontemporal."""
    i32 = ir.IntegerType.get_signless(32)
    ty = i32 if words == 1 else ir.VectorType.get([words], i32)
    ptr = llvm.IntToPtrOp(ir.Type.parse("!llvm.ptr<1>"), as_ir_value(fx.Int64(addr)))
    return llvm.LoadOp(
        ty, ptr.result, alignment=4 * words, nontemporal=nt or None
    ).result

hw_rsq(x)

v_rsq_f32 (~1 ulp, no libm range fixups).

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def hw_rsq(x):
    """v_rsq_f32 (~1 ulp, no libm range fixups)."""
    return _hw_f32("llvm.amdgcn.rsq.f32", x)

kernel_symbol(stem, **params)

Kernel symbol that profilers demangle to atom::<stem>_<params>. The amdhsa assembler rejects :: in a symbol, so it is Itanium-mangled, as aiter's _ZN5aiter...E kernels are.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def kernel_symbol(stem, **params):
    """Kernel symbol that profilers demangle to ``atom::<stem>_<params>``. The
    amdhsa assembler rejects ``::`` in a symbol, so it is Itanium-mangled, as
    aiter's ``_ZN5aiter...E`` kernels are."""
    name = f"{stem}_{kernel_signature(**params)}"
    return f"_ZN4atom{len(name)}{name}E"

lane_gather(v, src_lane)

Lane src_lane's value of v, a source lane a lane (ds_bpermute).

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def lane_gather(v, src_lane):
    """Lane ``src_lane``'s value of v, a source lane a lane (ds_bpermute)."""
    return fx.Int32(
        rocdl.ds_bpermute(T.i32, fx.Int32(src_lane) * 4, fx.Int32(v).ir_value())
    )

lanes_below(bal, lane)

How many of the lanes in ballot bal are below lane.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def lanes_below(bal, lane):
    """How many of the lanes in ballot ``bal`` are below ``lane``."""
    return popcount(bal & ((fx.Int64(1) << fx.Int64(lane)) - 1))

ld_dev(ptr, i, words=1)

words i32 (1, 2 or 4) of a buffer from word i, at device scope (past the per-XCD L2).

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def ld_dev(ptr, i, words=1):
    """``words`` i32 (1, 2 or 4) of a buffer from word ``i``, at device scope
    (past the per-XCD L2)."""
    return bo.buffer_load(
        rsrc(ptr), i, vec_width=words, dtype=T.i32, cache_modifier=CM_DEV
    )

ld_i32(ptr, i)

Word i of a buffer, a plain Int32 load.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def ld_i32(ptr, i):
    """Word ``i`` of a buffer, a plain Int32 load."""
    return fx.Int32(bo.buffer_load(rsrc(ptr), i, vec_width=1, dtype=T.i32))

lds_bytes(struct)

The LDS an fx.struct class takes, alignment included.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def lds_bytes(struct) -> int:
    """The LDS an ``fx.struct`` class takes, alignment included."""
    return struct.__dsl_size_of__()

load_ptr64(table, i)

Entry i of an i64 table in memory, wave-uniform (each half through uniform): a peer's buffer base, a kernel argument block's pointer.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def load_ptr64(table, i):
    """Entry ``i`` of an i64 table in memory, wave-uniform (each half through
    ``uniform``): a peer's buffer base, a kernel argument block's pointer."""
    pw = fx.Vector(bo.buffer_load(rsrc(table), i * 2, vec_width=2, dtype=T.i32))
    return (fx.Int64(uniform(pw[1])) << 32) | fx.Int64(fx.Uint32(uniform(pw[0])))

memrealtime()

s_memrealtime: the 100 MHz device clock (no FlyDSL wrapper).

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def memrealtime():
    """s_memrealtime: the 100 MHz device clock (no FlyDSL wrapper)."""
    return fx.Int64(llvm.call_intrinsic(T.i64, "llvm.amdgcn.s.memrealtime", [], [], []))

mfma_fp8(a, b, c)

16x16x32 fp8 x fp8 MFMA, unscaled: a / b an i64 of 8 E4M3 each.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def mfma_fp8(a, b, c):
    """16x16x32 fp8 x fp8 MFMA, unscaled: ``a`` / ``b`` an i64 of 8 E4M3 each."""
    return fx.Vector(
        rocdl.mfma_f32_16x16x32_fp8_fp8(T.vec(4, T.f32), [a, b, c, 0, 0, 0])
    )

permlane_swap(off, x, y)

v_permlane{32,16}_swap on registers (x, y): off 32 trades x's upper-half lanes with y's lower-half lanes; off 16 trades x's odd 16-lane rows with y's even rows (each within its half). -> (x', y').

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def permlane_swap(off, x, y):
    """v_permlane{32,16}_swap on registers (x, y): off 32 trades x's upper-half
    lanes with y's lower-half lanes; off 16 trades x's odd 16-lane rows with y's
    even rows (each within its half). -> (x', y')."""
    swap = rocdl.permlane32_swap if off == 32 else rocdl.permlane16_swap
    pr = swap(
        llvm.StructType.get_literal([T.i32, T.i32]),
        as_ir_value(fx.Int32(x)),
        as_ir_value(fx.Int32(y)),
        False,
        False,
    )
    return tuple(fx.Int32(llvm.extractvalue(T.i32, pr, [j])) for j in range(2))

readlane(v, src_lane)

Lane src_lane's value of v (wave-uniform).

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def readlane(v, src_lane):
    """Lane ``src_lane``'s value of v (wave-uniform)."""
    bits = v.bitcast(fx.Int32) if isinstance(v, fx.Float32) else fx.Int32(v)
    r = fx.Int32(rocdl.readlane(T.i32, bits, fx.Int32(src_lane)))
    return r.bitcast(fx.Float32) if isinstance(v, fx.Float32) else r

row_live(batch_ids, k)

Whether row k of the step is a request's: its batch_id_per_q_token entry, -1 on a CUDA-graph pad row (wave-uniform for a uniform k). A pad row runs like any other but joins no decision another row's work depends on.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def row_live(batch_ids, k):
    """Whether row k of the step is a request's: its ``batch_id_per_q_token``
    entry, -1 on a CUDA-graph pad row (wave-uniform for a uniform k). A pad row
    runs like any other but joins no decision another row's work depends on."""
    return uniform(ld_i32(batch_ids, k)) >= 0

row_shr(v, lane, k)

DPP row_shr:k of an f32: lane - k of the same 16-lane row, else 0.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def row_shr(v, lane, k):
    """DPP row_shr:k of an f32: lane - k of the same 16-lane row, else 0."""
    moved = lane_gather(v.bitcast(fx.Int32), fx.max(lane - k, 0)).bitcast(fx.Float32)
    return fx.Float32((lane % 16 >= k).select(moved, fx.Float32(0.0)))

row_sum(red, r, t, waves=None)

Row r, token t of the waves' 16x16 MFMA accumulators (wave w's at red + (w * 64 + lane) * 4), summed in wave order from 0 (waves: which, in order; all of them by default).

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def row_sum(red, r, t, waves=None):
    """Row r, token t of the waves' 16x16 MFMA accumulators (wave w's at ``red``
    + (w * 64 + lane) * 4), summed in wave order from 0 (``waves``: which, in
    order; all of them by default)."""
    tot = fx.Float32(0.0)
    for w in waves if waves is not None else range(WAVES):
        tot = tot + fx.ptr_load(red + ((w * 64 + 16 * (r // 4) + t) * 4 + r % 4))
    return tot

rows_to_lds(tid, src, rows, row_words, dst, dst_row)

rows rows of row_words words (a multiple of 4) read at device scope from address src -> LDS dst, a row every dst_row words: 16 B a lane, the loads batched (batched_rounds).

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def rows_to_lds(tid, src, rows, row_words, dst, dst_row):
    """``rows`` rows of ``row_words`` words (a multiple of 4) read at device scope
    from address ``src`` -> LDS ``dst``, a row every ``dst_row`` words: 16 B a
    lane, the loads batched (``batched_rounds``)."""
    assert row_words % 4 == 0, row_words
    batched_rounds(
        tid, rows * row_words // 4,
        lambda v: fx.Vector(ld_dev(src, v * 4, 4)),
        lambda v, w: fx.ptr_store(
            w, dst + (v * 4 // row_words * dst_row + v * 4 % row_words)
        ),
    )  # fmt: skip

traced(fn)

Apply flydsl's AST rewriting to a helper, so its while / if over traced values lower to scf ops. Kernels rewrite only their own body.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def traced(fn):
    """Apply flydsl's AST rewriting to a helper, so its ``while`` / ``if`` over
    traced values lower to scf ops. Kernels rewrite only their own body."""
    return ASTRewriter.transform(fn)

unlikely(cond)

cond marked cold (llvm.expect): LLVM lays the branch out of the hot path. A rare path's code inline among the hot stages costs them even when it never runs (the long-context selection: S = 16, 3k context +1.4 us).

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def unlikely(cond):
    """``cond`` marked cold (llvm.expect): LLVM lays the branch out of the hot
    path. A rare path's code inline among the hot stages costs them even when it
    never runs (the long-context selection: S = 16, 3k context +1.4 us)."""
    return fx.Boolean(
        llvm.call_intrinsic(
            ir.IntegerType.get_signless(1),
            "llvm.expect.i1",
            [as_ir_value(cond), as_ir_value(fx.Boolean(False))],
            [],
            [],
        )
    )

wave_incl_scan(v, lane)

Inclusive prefix sum of an Int32 over the wave, in lane order.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def wave_incl_scan(v, lane):
    """Inclusive prefix sum of an Int32 over the wave, in lane order."""
    blk = v
    for off in (1, 2, 4, 8, 16, 32):
        o = _xpartner(blk, off, lane)
        v = v + ((lane & off) != 0).select(o, 0)
        blk = blk + o
    return v

xred(v, off, op)

op(v, lane ^ off) for a symmetric op; 32 / 16 take both halves of one swap.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def xred(v, off, op):
    """op(v, lane ^ off) for a symmetric op; 32 / 16 take both halves of one swap."""
    if off < 16:
        return op(v, xshfl(v, off))
    is_f = isinstance(v, fx.Float32)
    x = v.bitcast(fx.Int32) if is_f else fx.Int32(v)
    a, b = permlane_swap(off, x, x)
    if is_f:
        return op(a.bitcast(fx.Float32), b.bitcast(fx.Float32))
    return op(type(v)(a), type(v)(b))

xshfl(v, off)

Value of lane lane ^ off: offsets 32 / 16 via v_permlane*_swap, in-row offsets via DPP (VALU latency, not LDS). Powers of two only: any other offset would take the lane ^ 1 path.

Source code in vllm/models/kimi_k3/amd/specialized_decode/mono/common/ops.py
def xshfl(v, off):
    """Value of lane ``lane ^ off``: offsets 32 / 16 via v_permlane*_swap, in-row
    offsets via DPP (VALU latency, not LDS). Powers of two only: any other
    offset would take the lane ^ 1 path."""
    assert off in (1, 2, 4, 8, 16, 32), off
    if off >= 16:
        return v.shuffle_xor(off, 64)
    is_f = isinstance(v, fx.Float32)
    x = v.bitcast(fx.Int32) if is_f else fx.Int32(v)
    if off == 8:
        y = fx.Int32(update_dpp_i32(x, x, 0x118, 0xF, 0xC, False))
        y = fx.Int32(update_dpp_i32(y, x, 0x108, 0xF, 0x3, False))
    elif off == 4:
        y = fx.Int32(update_dpp_i32(x, x, 0x114, 0xF, 0xA, False))
        y = fx.Int32(update_dpp_i32(y, x, 0x104, 0xF, 0x5, False))
    elif off == 2:
        y = fx.Int32(update_dpp_i32(x, x, 0x4E, 0xF, 0xF, False))
    else:
        y = fx.Int32(update_dpp_i32(x, x, 0xB1, 0xF, 0xF, False))
    return y.bitcast(fx.Float32) if is_f else y